Intel® Hyperflex™ Architecture High-Performance Design Handbook

ID 683353
Date 10/04/2021
Public
Document Table of Contents

2.1. High-Speed Design Methodology

Migrating a design to the Intel® Hyperflex™ architecture requires implementation of high-speed design best practices to obtain the most benefit and preserve functionality. The Intel® Hyperflex™ architecture FPGA high-speed design methodology proscribes latency-insensitive designs that support additional pipeline stages, and avoid performance-limiting loops. The following high-speed design best practices produce the most benefit for Intel® Hyperflex™ FPGAs:
  • Set a high-speed target
  • Experiment and iterate
  • Compile design components individually
  • Optimize design sub-modules
  • Avoid broadcast signals
The following sections describe specific RTL design techniques that enable Hyper-Retiming, Hyper-Pipelining, and Hyper-Optimization in the Intel® Quartus® Prime Pro Edition software.

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