2.3.2. Pipelining and Latency
If re-targeting an Intel® Hyperflex™ architecture FPGA doubles the fMAX requirement to 550 MHz, the path on the right side of the figure shows how an additional pipeline stage retimes. The path now achieves 555 MHz, due to the limits of the 1.8 ns delay. The data requires four cycles to propagate through the register pipeline. Four cycles at 550 MHz equals 7.273 ns to propagate through the pipeline.
To maintain the time to propagate through the pipeline with four stages compared to three, meet the 10.909 ns delay of the first version by increasing the fMAX of the second version to 367 MHz. This technique results in a 33% increase from 275 MHz.
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