Intel® Hyperflex™ Architecture High-Performance Design Handbook

ID 683353
Date 10/04/2021
Document Table of Contents

2.2. Hyper-Retiming (Facilitate Register Movement)

The Retime stage of the Fitter can balance register chains by retiming (moving) ALM registers into Hyper-Registers in the routing fabric. The Retime stage also performs sequential optimization by moving registers backward and forward across combinational logic. By balancing the propagation delays between each stage in a series of registers, retiming shortens the critical paths, reduces the clock period, and increases the frequency of operation.

The Retime stage then runs during Fitter processing to move the registers into ideal Hyper-Register locations. This Hyper-Retiming process requires minimal effort, while resulting in 1.1 – 1.3x performance gain.

In Moving Registers across LUTs, registers on the left show before retiming, with the worst case delay of two LUTs. Registers on the right show after retiming, with the worst case delay of one LUT.

Figure 6. Moving Registers across LUTs

When the Compiler cannot retime a register, this is a retiming restriction. Such restrictions limit the design’s fMAX. Minimize retiming restrictions in performance-critical parts of your designs to achieve the highest performance.

There are a variety of design conditions that limit performance. Limitations can relate to hardware characteristics, software behavior, or the design characteristics. Use the following design techniques to facilitate register retiming and avoid retiming restrictions:

  • Avoid asynchronous resets, except where necessary. Refer to the Reset Strategies section.
  • Avoid synchronous clears. Synchronous clears are usually broadcast signals that are not conducive to retiming.
  • Use wildcards or names in timing constraints and exceptions. Refer to the Timing Constraint Considerations section.
  • Avoid single cycle (stop/start) flow control. Examples are clock enables and FIFO full/empty signals. Consider using valid signals and almost full/empty, respectively.
  • Avoid preserve register attributes. Refer to the Retiming Restrictions and Workarounds section.
  • For information about adding pipeline registers, refer to the Hyper-Pipelining (Add Pipeline Registers) section.
  • For information about addressing loops and other RTL restrictions to retiming, refer to the Hyper-Optimization (Optimize RTL) section.

The following sections provide design techniques to facilitate register movement in specific design circumstances.

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