188.8.131.52. Insufficient Registers Example
The following screenshots show the relevant parts of the Retiming Limit Details report and the logic in the critical chain.
The Retiming Limit Details report indicates that the performance of the clk domain fails to meet the timing requirement .
The circuit has an inefficient crossbar switch implemented with one stage of input registers, one stage of output registers, and purely combinational logic to route the signals. The input and output registers have asynchronous resets. Because the multiplexer in the crossbar is not pipelined, the implementation is inefficient and the performance is limited.
In Critical Chain in Post-Fit Technology Map Viewer, the critical chain goes from the input register, through a combinational logic cloud, to the output register. The critical chain contains only one register-to-register path.
In Critical Chain with Insufficient Registers Reported During Hyper-Retiming, line 1 shows a timing restriction in the Path Info column. Line 33 also lists a retiming restriction. The asynchronous resets on the two registers cause the retiming restrictions.
Correlation Between Critical Chain Elements and Technology Map Viewer shows the correlation between critical chain elements and the Technology Map Viewer examples.
|Line Numbers in Critical Chain Report||Circuit Element in the Technology Map Viewer|
|1-2||din_reg source register and its output|
|3-9||FPGA routing fabric between din_reg and Mux_0~20, the first stage of mux in the crossbar|
|10-11||Combinational logic implementing Mux_0~20|
|12-15||Routing between Mux_0~20 and Mux_0~24, the second stage of mux in the crossbar|
|16-17||Combinational logic implementing Mux0~24|
|18-20||Routing between Mux0~24 and Mux0~40, the third stage of mux in the crossbar|
|21-22||Combinational logic implementing Mux_0~40|
|23-29||Routing between Mux_0~40 and Mux_0~41, the fourth stage of mux in the crossbar|
|30-31||Combinational logic implementing Mux_0~41|
|32-33||dout_reg destination register|
In the critical chain report in Critical Chain with Insufficient Registers Reported During Hyper-Retiming, there are 11 lines that list bypass Hyper-Register in the Register column. Bypassed Hyper-Register indicates the location of a Hyper-Register for use if there are more registers in the chain, or if there are no restrictions on the endpoints. If there are no restrictions on the endpoints, the Compiler can retime the endpoint registers, or retime other registers from outside the critical chain into the critical chain. If the RTL design contains more registers through the crossbar switch, there are more registers that the Compiler can retime. Fast Forward compilation can also insert more registers to increase the performance.
In the critical chain report, lines 2 to 32 list "Long Path (Critical)" in the Path Info column. This indicates that the path is too long to run above the listed frequency. The "Long Path" designation is also related to the Short Path/Long Path type of critical chain. Refer to the Short Path/Long Path section for more details. The (Critical) designation exists on one register-to-register segment of a critical chain. The (Critical) designation indicates that the register-to-register path is the most critical timing path in the clock domain.
The Register ID column contains a "#1" on line 1, and a "#2" on line 33. The information in the Register ID column helps interpret more complex critical chains. For more details, refer to Complex Critical Chains section.
The Element column in Critical Chain with Insufficient Registers Reported During Hyper-Retiming shows the name of the circuit element or routing resource at each step in the critical chain. You can right-click the names to copy them, or cross probe to other parts of the Intel® Quartus® Prime software with the Locate option.