Intel® Hyperflex™ Architecture High-Performance Design Handbook

ID 683353
Date 10/04/2021

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3.2. Design Assistant Design Rule Checking

The Intel® Quartus® Prime Design Assistant increases productivity by reducing the total number of design iterations for design closure, and by minimizing the time in each iteration with targeted rule checks and guidance at each stage of compilation.

The Design Assistant detects and helps you to resolve design rule violations by providing recommendations for correction and pathways to the violation source. Avoiding design rule violations improves the reliability, timing performance, and logic utilization of your design.

When enabled, Design Assistant automatically reports any violations against a standard set of Intel FPGA-recommended design guidelines 1. You can run Design Assistant automatically during compilation, and report violations detected throughout the compilation process.

Figure 84. Design Assistant Recommends Corrections for Design Rule Violations

Alternatively, you can run Design Assistant in analysis mode, which allows you to launch Design Assistant checks from other Intel® Quartus® Prime tools, such as Chip Planner. For some rules, Design Assistant supports cross-probing to the Timing Analyzer and Intel® Quartus® Prime design visualization tools for root cause analysis and correction.

You can specify which rules Design Assistant checks, thus eliminating the rule checks that are unimportant for your design.

1 A set of default rules ensures design health without significant runtime increase.