Intel® Hyperflex™ Architecture High-Performance Design Handbook

ID 683353
Date 10/04/2021

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7.1.3. Clock Management

After black-boxing appropriate logic, ensure that all registers in the design are still receiving a clock signal. All the PLLs must still be present. Identify any clock existing a black-boxed module. If this occurs in your design, recreate this clock. Failure to recreate the clock marks any register downstream as unclocked. This condition changes the logic function of your design, because synthesis can remove registers that do not receive a clock. Examine the clock definitions in the .sdc file to determine if this file specifies a clock definition in one of the black-boxed modules. Looking at a particular module, several conditions can occur:

  • There is a clock definition in that module:
    • Does the clock signal reach the primary output of the module and a clock pin of a register downstream of the module?
      • No: this clock is completely internal and no action required.
      • Yes: create a clock on the output pin of that module matching the definition in the .sdc.
  • There is no clock definition in that module:
    • Is there a clock feedthrough path in that module?
      • No: there is no action required.
      • Yes: create a new clock on the feedthrough output pin of the module.