Intel® Hyperflex™ Architecture High-Performance Design Handbook

ID 683353
Date 10/04/2021

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2.2.5. Clock Synchronization Strategies

Use a simple synchronization strategy to reach maximum speeds in Intel® Hyperflex™ architecture FPGAs. Adding latency on paths with simple synchronizer crossings is straightforward. However, adding latency on other crossings is more complex.

Simple Clock Domain Crossingshows a simple synchronization scheme with a path from one register of the first domain (blue), directly to a register of the next domain (red).

Figure 12. Simple Clock Domain Crossing

To add latency in the red domain for retiming, add the registers as Adding Latency to Simple Clock Domain Crossing shows.

Figure 13. Adding Latency to Simple Clock Domain Crossing

Clock Domain Crossing at Multiple Locations shows a domain crossing structure that is not optimum in Intel® Hyperflex™ architecture FPGAs, but exists in designs that target other device families. The design contains some combinational logic between the blue clock domain and the red clock domain. The design does not properly synchronize the logic and you cannot add registers flexibly. The blue clock domain drives the combinational logic and the logic contains paths that the red domain launches.

Figure 14. Clock Domain Crossing at Multiple Locations

Adding Latency at Multiple Clock Domain Crossing Locations shows adding latency at the boundary of the red clock domain, without adding registers on a red to red domain path. Otherwise, the paths become unbalanced (with respect to the cycle behavior on clock edges), potentially changing design functionality. Although possible, adding latency in this scenario is risky. Thoroughly analyze the various paths before adding latency.

Figure 15. Adding Latency at Multiple Clock Domain Crossing Locations

For Intel® Hyperflex™ architecture FPGAs, synchronize the clock crossing paths before entering combinational logic. Adding latency is then more simple when you compare with the previous example.

Clock Domain Synchronization Improvement shows blue domain registers synchronizing to the red domain before entering the combinational logic. This method allows safe addition of pipeline registers in front of synchronizing registers, without contacting a red to red path inadvertently. Implement this synchronization method for the highest performance in Intel® Hyperflex™ architecture FPGAs.

Figure 16. Clock Domain Synchronization Improvement