220.127.116.11.1. Implementing Clock Gating
- Reset Release Intel® FPGA IP—holds your design in reset until configuration is complete by gating clocks, resets, or write enables. This IP outputs the nINIT_DONE signal. When nINIT_DONE is low, the device is no longer in configuration mode.
- Clock Control Intel® FPGA IP—uses the inverted nINIT_DONE signal as a clock enable signal.
Follow these steps to implement clock gating:
- Open a design in the Intel® Quartus® Prime software.
- In IP Catalog, type reset release in the search field, and double-click the Reset Release Intel® FPGA IP .
- Specify appropriate parameters for your configuration in the parameter editor, and then click Generate HDL.
- Repeat steps 2 and 3 to add the Clock Control Intel® FPGA IP to your project. Prior to IP generation, specify the following options for the IP in the parameter editor:
- Under Clock Gating, turn on the Clock Enable option.
- For Clock Enable Type, select Root Level.
- For Enable Register Mode, select Negative Latch.
- Connect the Reset Release and Clock Control Intel® FPGA IP together:
- To gate the clocks, use inverted nINIT_DONE as the enable input to the Clock Control Intel® FPGA IP.
- If initial conditions are required, Intel recommends that the Clock Control Intel® FPGA IP also use root clock gating.
The following figure shows proper connections between the Reset Release and Clock Control Intel® FPGA IP to ensure accurate initial conditions after configuration:Figure 19. Connections between the Reset Release (reset_release) and Clock Control (clock_control) Intel® FPGA IP Cores
The Clock Control Intel® FPGA IP uses the ena signal to perform the clock gating function. The clock signal on the output of the Clock Control Intel® FPGA IP is then safe for use with the initialized registers (ALM and Hyper-Registers).
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