Intel® Hyperflex™ Architecture High-Performance Design Handbook

ID 683353
Date 10/04/2021
Document Table of Contents Launching Design Assistant from Chip Planner

You can run Design Assistant directly from Chip Planner to assist when optimizing the floorplan in the tool. When you launch Design Assistant from the Chip Planner, Design Assistant is preset to check only the FLP (floorplanning) Design Assistant rules. Follow these steps to run the Design Assistant from the Chip Planner:
  1. Run any stage of the Compiler. You must run at least the Analysis & Elaboration stage before running Design Assistant from Chip Planner.
  2. Click Tools > Chip Planner.
    Figure 91. Report DRC Dialog Box in Chip Planner
  3. In Chip Planner Tasks pane, click Report DRC under Design Assistant. The Report DRC (design rule check) dialog box appears.
  4. Under Rules, disable any rules that are not important to your analysis by removing the check mark.
  5. Consider whether to adjust rule parameter values in the Parameters field.
  6. Under Output, confirm the Report panel name and optionally specify an output File name.
  7. Click Run. The Results reports generate and appear in the Report pane and in the Compilation Report.
    Figure 92. Rule Violations in Chip Planner Reports Pane
    Figure 93. Chip Planner Rule Violations in Main Compilation Report

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