Intel® Hyperflex™ Architecture High-Performance Design Handbook

ID 683353
Date 10/04/2021
Document Table of Contents

2.2.6. Metastability Synchronizers

The Compiler detects registers that are part of a synchronizer chain. The Compiler cannot retime the registers in a synchronizer chain. To allow retiming of the registers in a synchronizer chain, add more pipeline registers at clock domain boundaries.

The default metastability synchronizer chain length for Intel® Hyperflex™ architecture FPGAs is three. The Critical Chain report marks the registers that metastability requires with REG (Metastability required) text.

If your design includes two-register chains as synchronizers, you can specify the following setting to modify the default chain length from 3 to 2:

  1. Click Assignments > Settings.
  2. Click Compiler Settings under Category.
  3. Click the Advanced Settings (Synthesis) button.
  4. For Synchronization Register Chain Length, type 2 in the Setting column.

Alternatively, you can specify this setting in the .qsf file:

set_instance_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 \
     -to * -entity <top_module_name>

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