Intel® Hyperflex™ Architecture High-Performance Design Handbook

ID 683353
Date 10/04/2021
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5.1. Setting the dont_merge Synthesis Attribute

You can set the dont_merge attribute in your HDL code, as shown in the following examples.
Table 11.  Setting the attribute in HDL code dont_merge prevents the my_reg register from merging.
HDL Code
Verilog HDL
reg my_reg /* synthesis dont_merge */;
Verilog-2001 and SystemVerilog
(* dont_merge *) reg my_reg;
VHDL
signal my_reg : stdlogic;
attribute dont_merge : boolean;
attribute dont_merge of my_reg : signal is true;