2.2.3. Preserving Registers During Synthesis
You can specify entity-level assignments and synthesis attributes to preserve specific registers during synthesis processing.
For example, the Preserve Registers in Synthesis assignment preserves the register that you assign during synthesis, without restricting Hyper-Retiming optimization. Similarly, you can specify the dont_merge or preserve_syn_only synthesis attributes to preserve registers without restricting retiming optimization, as the following example shows.
logic hip_data; /* synthesis preserve_syn_only */ (*preserve_syn_only*) logic hip_data;
The Preserve Registers assignment also preserves registers, but does not allow Hyper-Retimer optimization of the registers that you assign. This assignment can be useful when you want to preserve a register for debugging observability.
Specify any of the following synthesis preservation assignments by clicking Assignments > Assignment Editor, by modifying the .qsf file, or by specifying synthesis attributes in your RTL.
|Assignment||Description||Allows Fitter Optimization?||Assignment Syntax|
|Preserve Registers in Synthesis||Prevents removal of registers during synthesis. This settings does not affect retiming or other optimizations in the Fitter.||Yes||
|Preserve Fan-Out Free Register Node||Prevents removal of assigned registers without fan-out during synthesis.
The PRESERVE_FANOUT_FREE_NODE assignment cannot preserve a fanout-free register that has no fanout inside the Verilog HDL or VHDL module in which you define it. To preserve these fanout-free registers, implement the noprune pragma in the source file:
If there are multiple instances of this module, with only some instances requiring preservation of the fanout-free register, set a dummy pragma on the register in the HDL and also set the PRESERVE_FANOUT_FREE_NODE assignment. This dummy pragma allows the register synthesis to implement the assignment. For example, set the following dummy pragma for a register r in Verilog HDL:
|Preserve Registers||Prevents removal and sequential optimization of assigned registers during synthesis. Sequential netlist optimizations can eliminate redundant registers and registers with constant drivers.||No||
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