3.1. Compiling Submodules Independently
You can independently compile submodules of a larger design. Compiling a larger submodule independently allows you to obtain submodule performance information, and to optimize the submodule for better performance. Depending on your goals in compiling the submodule, you may choose to handle the I/Os differently, as the following techniques describe:
- If you require additional Hyper-Optimization for the submodule during compilation, instantiate the submodule within a wrapper, adding two or more register stages at each input and output. This technique allows retiming of those additional registers into the circuit. If the Compiler retimes the additional registers into the submodule, then you can modify the full design to provide extra registers to the submodule. This method is useful when testing Hyper-Optimization on your submodule to determine the impact of retiming when the submodule is part of the larger design.
- If you do not require further submodule Hyper-Optimization, but want to isolate a module to save compile time and mimic the module timing budget in the full design, define virtual pin constraints to enable retiming of the registers connecting directly to the submodule. Specify appropriate set_input_delay or set_ouput_delay SDC constraints to account for the clock skew of the internal clock tree. Account for the clock skew of the internal clock tree by specifying either a reference_pin or a static maximum constraint, according to the following guidelines and examples:
|clock||Specify the internal clock domain name (no virtual clock). This argument causes the Compiler to treat external and internal clocks the same, allowing retiming of I/O registers no longer on the boundary.|| reference_pin argument:
static maximum constraint:
|delay||Specify one of the following to account for the clock skew of the internal clock tree:
set_input_delay -clock [get_clocks clk_in] \ 0 [get_ports data] \ -reference_pin [get_pins [int_reg|clk]
set insert_delay 1.3 set_input_delay -clock [get_clocks clk_in] \ $insert_delay [get_ports data]
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