22.214.171.124. Ternary Adders
Ternary Adder RTL Code
module ternary_adder (CLK, A, B, C, OUT); parameter WIDTH = 16; input [WIDTH-1:0] A, B, C; input CLK; output [WIDTH-1:0] OUT; wire [WIDTH-1:0] sum1; reg [WIDTH-1:0] sumreg1; // 3-bit additions assign sum1 = A + B + C; assign OUT = sumreg1; // Registers always @ (posedge CLK) begin sumreg1 <= sum1; end endmodule
This increase in device resource use occurs because the Intel® Hyperflex™ architecture ALM does not have a shared arithmetic mode that previous FPGA technologies have. The ALM in shared arithmetic mode can implement a three-input add in the ALM. By contrast, the Intel® Hyperflex™ architecture ALM can implement only a two-input add in the ALM.
In shared arithmetic mode, the Intel® Arria® 10 ALM allows a three-input adder to use three adaptive LUT (ALUT) inputs: CIN, SHAREIN, COUT, SUMOUT, and SHAREOUT. The absence of the shared arithmetic mode restricts ALM use with only two ALUT inputs: CIN, COUT and SUMOUT. The figure below shows the resulting implementation of a ternary adder on both Intel® Arria® 10 and Intel® Hyperflex™ architecture FPGAs.
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