Intel® Hyperflex™ Architecture High-Performance Design Handbook

ID 683353
Date 10/04/2021

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7.1. Design Migration and Performance Exploration

You can migrate to an Intel® Hyperflex™ architecture FPGA to evaluate performance improvement. Migrating a design for an Intel® Hyperflex™ architecture FPGA requires only minor changes. However, you can apply additional non-required changes for further performance improvement. This performance improvement helps you to close timing and add functionality to your design.

Any device migration typically requires some common design changes. These changes include updating PLLs, high-speed I/O pins, and other device resources. The Intel® Hyperflex™ architecture versions of these components have the same general functionality as in previous device families. However, the Intel® Hyperflex™ architecture IP components include features to enable higher operational speeds:

  • DSP blocks include pipeline registers and support a floating point mode.
  • Memory blocks include additional logic for coherency, and width restrictions.
The high level steps in the migration process are:
  1. Select for migration a lower-level block in the design, without any specialized IP.
  2. Black-box any special IP component and only retain components that the current level requires. Only retain the following key blocks for core performance evaluation:
    • PLLs for generating clocks
    • Core blocks (logic, registers, memories, DSPs)
      Note: If you migrate a design from a previous version of the Intel® Quartus® Prime software, some Intel® FPGA IP may require replacement if incompatible with the current software version. For example, you cannot upgrade IP based transceivers that a different between different device families.
  3. Maintain module port definitions when black-boxing components. Do not simply remove the source file from the project.
  4. Specify the port definition and direction of every component that the design uses to the synthesis software. Failure to define the ports results in compilation errors.
  5. During design synthesis, review the error messages and correct any missing port or module definitions.

The easiest way to black-box a module is to empty the functional content. The following examples show black-boxing in Verilog HDL or VHDL.