7.1. Design Migration and Performance Exploration
Any device migration typically requires some common design changes. These changes include updating PLLs, high-speed I/O pins, and other device resources. The Intel® Hyperflex™ architecture versions of these components have the same general functionality as in previous device families. However, the Intel® Hyperflex™ architecture IP components include features to enable higher operational speeds:
- DSP blocks include pipeline registers and support a floating point mode.
- Memory blocks include additional logic for coherency, and width restrictions.
- Select for migration a lower-level block in the design, without any specialized IP.
- Black-box any special IP component and only retain components that the current level requires. Only retain the following key blocks for core performance evaluation:
- PLLs for generating clocks
- Core blocks (logic, registers, memories, DSPs)
Note: If you migrate a design from a previous version of the Intel® Quartus® Prime software, some Intel® FPGA IP may require replacement if incompatible with the current software version. For example, you cannot upgrade IP based transceivers that a different between different device families.
- Maintain module port definitions when black-boxing components. Do not simply remove the source file from the project.
- Specify the port definition and direction of every component that the design uses to the synthesis software. Failure to define the ports results in compilation errors.
- During design synthesis, review the error messages and correct any missing port or module definitions.
The easiest way to black-box a module is to empty the functional content. The following examples show black-boxing in Verilog HDL or VHDL.
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