Intel® Hyperflex™ Architecture High-Performance Design Handbook

ID 683353
Date 10/04/2021

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Document Table of Contents

4.1.1. Step 1: Compile the Base Design

Follow these steps to compile the base design of the median project:
  1. In the Intel® Quartus® Prime Pro Edition software, click File > Open Project and select the Median_filter_<version>/Base/median.qpf project file. The base version of the design example opens.
  2. To compile the base design, click Compile Design on the Compilation Dashboard. By default, the Fast Forward Timing Recommendations stage runs during the Fitter, and generates detailed recommendations in the Fast Forward Details report.
  3. Click the report icon for Fast Forward Timing Closure Recommendations. In the Fast Forward Details report, view the compilation results for the Clk clock domain.
    Figure 98. Fast Forward Details Report

    The report indicates a Base Performance of 188 MHz, with the following design conditions limiting further optimization:

    • The design contains asynchronous resets (clears).
    • Additional pipeline stages (registers) can improve performance.
    • Short path and long path combinations limit further optimization.

    The following steps describe implementation of these recommendations in the design RTL.