Intel® Agilex™ F-Series and I-Series LVDS SERDES User Guide

ID 721819
Date 11/30/2022
Public
Document Table of Contents

5.1.5.1. LVDS SERDES Intel® FPGA IP General Settings

Table 12.  General Settings Tab
Parameter Value Description
Functional mode
  • TX
  • RX Non-DPA
  • RX DPA-FIFO
  • RX Soft-CDR

Specifies the functional mode of the interface.

Default is TX.

Number of channels
  • TX
    • Enable tx_outclock port = On—1 to 11
    • Enable tx_outclock port = Off—1 to 12
  • RX Non-DPA—1 to 12
  • RX DPA-FIFO—1 to 12
  • RX Soft-CDR—1 to 8

Specifies the number of serial channels in the interface.

Default is 1.

  • If you use a dedicated reference clock for the TX, RX soft-CDR, RX non-DPA, or RX DPA-FIFO, you must use one of the channels for the refclk pin. Use a dedicated reference clock to reduce jitter.
  • If you use a transmitter output clock, you must use one of the channels for the tx_outclock pin.

For an LVDS RX design, place the refclk pin on the same I/O bank as the receiver.

Data rate 150.0 to 1600.0

Specifies the data rate (in Mbps) of a single serial channel.

Default is 1000.0.

The data rate follows the I/O PLL VCO operating range. The maximum data rate depends on the device core speed grade.

SERDES factor 3, 4, 5, 6, 7, 8, 9, and 10

Specifies the serialization rate or deserialization rate for the LVDS interface.

Default is 10.

Use backwards-compatible port names
  • On
  • Off
Turn on to use legacy top-level names that are compatible with the ALTLVDS_TX and ALTLVDS_RX IPs.

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