1. Intel® Agilex™ F-Series and I-Series LVDS SERDES Overview
|Intel® Quartus® Prime Design Suite 22.1|
Intel® Agilex™ F-series and I-series devices support LVDS serializer/deserializer (SERDES) through the True Differential Signaling I/Os in the GPIO banks. The true differential I/Os are capable of supporting LVDS interfaces, including subsets such as:
- Any I/O standards using equivalent electrical specifications
Intel® Agilex™ F-series and I-series devices support SERDES on all True Differential Signaling GPIO banks with the following features:
- SERDES interfaces up to 1.6 Gbps.
- Differential 100-ohm OCT RD.
- Differential I/O reference clock for the I/O PLL that drives the SERDES.
- Dedicated transmitter and dedicated receiver differential pin pairs in each I/O bank with multiple usage modes options.
- In each I/O bank, there are 24 receiver channels with SERDES and DPA, and 24 transmitter channels with SERDES. The total number of SERDES channels varies across Intel® Agilex™ devices, depending on the total number of pins available in the package.
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