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1. Intel® Agilex™ F-Series and I-Series LVDS SERDES Overview
2. Intel® Agilex™ F-Series and I-Series High-Speed SERDES Architecture
3. Intel® Agilex™ LVDS SERDES Transmitter
4. Intel® Agilex™ LVDS SERDES Receiver
5. Intel® Agilex™ High-Speed LVDS I/O Implementation Guide
6. Intel® Agilex™ LVDS SERDES Timing
7. LVDS SERDES Intel® FPGA IP Design Examples
8. Intel® Agilex™ F-Series and I-Series High-Speed SERDES Design Guidelines
9. Intel® Agilex™ F-Series and I-Series High-Speed SERDES Troubleshooting Guidelines
10. Documentation Related to the Intel® Agilex™ F-Series and I-Series LVDS SERDES User Guide
11. Document Revision History for the Intel® Agilex™ F-Series and I-Series LVDS SERDES User Guide
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2. Intel® Agilex™ F-Series and I-Series High-Speed SERDES Architecture
Each GPIO bank in Intel® Agilex™ F-series and I-series devices consists of two sub-banks. Each sub-bank contains its own PLL, dynamic phase alignment (DPA), and SERDES circuitry blocks.
Channels | Total Pairs Per Bank | Channel Mode | Pairs Per Sub-Bank | |
---|---|---|---|---|
Top | Bottom | |||
Dedicated SERDES transmitter | 24 | Transmitter | 12 | 12 |
Dedicated SERDES receiver | 24 | DPA | 12 | 12 |
Non-DPA | 12 | 12 | ||
Soft-CDR | 4 | 8 |
Section Content
Intel Agilex GPIO Banks, SERDES, and DPA Locations
SERDES Blocks, Modes, and Clock Domains
Related Information
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