Intel® Agilex™ F-Series and I-Series LVDS SERDES User Guide

ID 721819
Date 11/30/2022

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

2. Intel® Agilex™ F-Series and I-Series High-Speed SERDES Architecture

Each GPIO bank in Intel® Agilex™ F-series and I-series devices consists of two sub-banks. Each sub-bank contains its own PLL, dynamic phase alignment (DPA), and SERDES circuitry blocks.
Table 2.  Differential Pairs and Channel Mode Support in Each Bank and Sub-BankThe SERDES transmitter and receiver channels are adjacent to each other. Refer to the device pin-out files for the exact location of the SERDES and Soft-CDR pins.
Channels Total Pairs Per Bank Channel Mode Pairs Per Sub-Bank
Top Bottom
Dedicated SERDES transmitter 24 Transmitter 12 12
Dedicated SERDES receiver 24 DPA 12 12
Non-DPA 12 12
Soft-CDR 4 8