Intel® Agilex™ F-Series and I-Series LVDS SERDES User Guide

ID 721819
Date 11/30/2022
Public
Document Table of Contents

5.1. LVDS SERDES Intel® FPGA IP

The LVDS SERDES IP configures the serializer/deserializer (SERDES) and dynamic phase alignment (DPA) blocks. The IP also supports LVDS channel placements, legality checks, and LVDS channel-related rule checks.

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