7.3. Combined LVDS SERDES IP Transmitter and Receiver Design Example
If your LVDS SERDES IP configuration implements a transmitter, the design example adds a DPA-FIFO receiver. If your LVDS SERDES IP configuration implements any of the receiver interfaces, the design example adds a transmitter.
Generating and Using the Design Example
To generate the combined transmitter and receiver design example from the source files, run the following command in the design example directory:
quartus_sh -t make_qii_design.tcl -system ed_synth_tx_rx
The TCL script creates a qii_ed_synth_tx_rx directory that contains the ed_synth_tx_rx.qpf project file. You can open and compile this project in the Intel® Quartus® Prime software.
For more information about make_qii_design.tcl arguments, run the following command:
quartus_sh -t make_qii_design.tcl -help
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