Intel® Agilex™ F-Series and I-Series LVDS SERDES User Guide

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ID 721819
Date 11/30/2022
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Document Table of Contents
Document Table of Contents x
1. Intel® Agilex™ F-Series and I-Series LVDS SERDES Overview 2. Intel® Agilex™ F-Series and I-Series High-Speed SERDES Architecture 3. Intel® Agilex™ LVDS SERDES Transmitter 4. Intel® Agilex™ LVDS SERDES Receiver 5. Intel® Agilex™ High-Speed LVDS I/O Implementation Guide 6. Intel® Agilex™ LVDS SERDES Timing 7. LVDS SERDES Intel® FPGA IP Design Examples 8. Intel® Agilex™ F-Series and I-Series High-Speed SERDES Design Guidelines 9. Intel® Agilex™ F-Series and I-Series High-Speed SERDES Troubleshooting Guidelines 10. Documentation Related to the Intel® Agilex™ F-Series and I-Series LVDS SERDES User Guide 11. Document Revision History for the Intel® Agilex™ F-Series and I-Series LVDS SERDES User Guide
1. Intel® Agilex™ F-Series and I-Series LVDS SERDES Overview x
1.1. High-Speed SERDES Usage Modes
2. Intel® Agilex™ F-Series and I-Series High-Speed SERDES Architecture x
2.1. Intel® Agilex™ GPIO Banks, SERDES, and DPA Locations 2.2. SERDES Blocks, Modes, and Clock Domains
3. Intel® Agilex™ LVDS SERDES Transmitter x
3.1. LVDS SERDES Transmitter Blocks 3.2. Serializer 3.3. Differential I/O Bit Position 3.4. Clocking the Differential Transmitters
3.2. Serializer x
3.2.1. Serializer Bypass for DDR and SDR Operations
3.4. Clocking the Differential Transmitters x
3.4.1. Transmitter Output Clock Parameters Settings
3.4.1. Transmitter Output Clock Parameters Settings x
3.4.1.1. Edge-Aligned tx_outclock to tx_out 3.4.1.2. Center-Aligned tx_outclock to tx_out
4. Intel® Agilex™ LVDS SERDES Receiver x
4.1. LVDS SERDES Receiver Blocks 4.2. Clocking the LVDS SERDES Receivers 4.3. LVDS SERDES Receiver Modes
4.1. LVDS SERDES Receiver Blocks x
4.1.1. Dynamic Phase Alignment Block 4.1.2. Synchronizer (DPA FIFO) 4.1.3. Data Realignment Block (Bit Slip) 4.1.4. Deserializer
4.2. Clocking the LVDS SERDES Receivers x
4.2.1. Receiver Input Clock Parameters Settings
4.2.1. Receiver Input Clock Parameters Settings x
4.2.1.1. Edge-Aligned inclock to rx_in 4.2.1.2. Center-Aligned inclock to rx_in
4.3. LVDS SERDES Receiver Modes x
4.3.1. Non-DPA Mode 4.3.2. DPA Mode 4.3.3. Soft-CDR Mode
5. Intel® Agilex™ High-Speed LVDS I/O Implementation Guide x
5.1. LVDS SERDES Intel® FPGA IP 5.2. LVDS Interface with External PLL Mode 5.3. LVDS SERDES IP Initialization and Reset
5.1. LVDS SERDES Intel® FPGA IP x
5.1.1. Release Information 5.1.2. LVDS SERDES Intel® FPGA IP Features 5.1.3. LVDS SERDES IP Usage Modes 5.1.4. Generating the LVDS SERDES Intel® FPGA IP 5.1.5. LVDS SERDES Intel® FPGA IP Parameter Settings 5.1.6. LVDS SERDES Intel® FPGA IP Signals
5.1.4. Generating the LVDS SERDES Intel® FPGA IP x
5.1.4.1. Intel® FPGA IP Generation Output
5.1.5. LVDS SERDES Intel® FPGA IP Parameter Settings x
5.1.5.1. LVDS SERDES Intel® FPGA IP General Settings 5.1.5.2. LVDS SERDES Intel® FPGA IP PLL Settings 5.1.5.3. LVDS SERDES Intel® FPGA IP Receiver Settings 5.1.5.4. LVDS SERDES Intel® FPGA IP Transmitter Settings 5.1.5.5. LVDS SERDES Intel® FPGA IP Clock Resource Summary
5.2. LVDS Interface with External PLL Mode x
5.2.1. IOPLL IP Signal Interface with LVDS SERDES IP 5.2.2. IOPLL Parameter Values for External PLL Mode 5.2.3. Connection between IOPLL IP and LVDS SERDES IP in External PLL Mode
5.3. LVDS SERDES IP Initialization and Reset x
5.3.1. Initializing the LVDS SERDES IP in Non-DPA Mode 5.3.2. Initializing the LVDS SERDES IP in DPA Mode 5.3.3. Resetting the DPA 5.3.4. Word Boundaries Alignment
5.3.4. Word Boundaries Alignment x
5.3.4.1. Aligning Word Boundaries
6. Intel® Agilex™ LVDS SERDES Timing x
6.1. LVDS SERDES Intel® FPGA IP Timing 6.2. LVDS SERDES Source-Synchronous Timing Budget
6.1. LVDS SERDES Intel® FPGA IP Timing x
6.1.1. I/O Timing Analysis 6.1.2. FPGA Timing Analysis 6.1.3. Timing Analysis for the External PLL Mode
6.1.1. I/O Timing Analysis x
6.1.1.1. Obtaining RSKM Report 6.1.1.2. Obtaining TCCS Report
6.2. LVDS SERDES Source-Synchronous Timing Budget x
6.2.1. Transmitter Channel-to-Channel Skew 6.2.2. Receiver Skew Margin
7. LVDS SERDES Intel® FPGA IP Design Examples x
7.1. LVDS SERDES IP Synthesizable Intel® Quartus® Prime Design Examples 7.2. LVDS SERDES IP Simulation Design Example 7.3. Combined LVDS SERDES IP Transmitter and Receiver Design Example 7.4. LVDS SERDES IP Dynamic Phase Shift Design Example
8. Intel® Agilex™ F-Series and I-Series High-Speed SERDES Design Guidelines x
8.1. Use PLLs in Integer PLL Mode for LVDS 8.2. Use High-Speed Clock from PLL to Clock SERDES Only 8.3. Pin Placement for Differential Channels 8.4. SERDES Pin Pairs for Soft-CDR Mode 8.5. Placing LVDS Transmitters and Receivers in the Same GPIO Bank
1. Intel® Agilex™ F-Series and I-Series LVDS SERDES Overview
2. Intel® Agilex™ F-Series and I-Series High-Speed SERDES Architecture
3. Intel® Agilex™ LVDS SERDES Transmitter
4. Intel® Agilex™ LVDS SERDES Receiver
5. Intel® Agilex™ High-Speed LVDS I/O Implementation Guide
6. Intel® Agilex™ LVDS SERDES Timing
7. LVDS SERDES Intel® FPGA IP Design Examples
8. Intel® Agilex™ F-Series and I-Series High-Speed SERDES Design Guidelines
9. Intel® Agilex™ F-Series and I-Series High-Speed SERDES Troubleshooting Guidelines
10. Documentation Related to the Intel® Agilex™ F-Series and I-Series LVDS SERDES User Guide
11. Document Revision History for the Intel® Agilex™ F-Series and I-Series LVDS SERDES User Guide

6.1.2. FPGA Timing Analysis

When you generate the LVDS SERDES IP, the IP generates the SERDES hardware clock settings and the core clock for IP timing analysis.
Table 34.  Clocks for the Transmitter and Receiver in Non-DPA and DPA-FIFO ModesBecause the frequency of LVDS fast clock is higher than the user core clock by the serialization factor, the IP also creates multicycle path constraints for proper timing analysis at the SERDES–core interface.
Clock Clock Name
Core clock <pll_instance_name>_*_outclk[*]
LVDS fast clock <pll_instance_name>_*_lvds_clk[*]
Table 35.  Clock for the Receiver in Soft-CDR Mode
Clock Clock Name
Core clock <lvds_instance_name>_core_ck_name_<channel_num>
DPA fast clock <lvds_instance_name>_dpa_ck_name_<channel_num>
To ensure proper timing analysis, instead of multicycle constraints, the IP creates clock settings at rx_out in the following format:
  • For rising edge data— <lvds_instance_name>_core_data_out_<channel_num>_<bit>
  • For falling edge data— <lvds_instance_name>_core_data_out_<channel_num>_<bit>_neg

With these proper clock settings, the Timing Analyzer can correctly analyze the timing of the LVDS SERDES–core interface transfer and within the core transfer.

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