Intel® Agilex™ F-Series and I-Series LVDS SERDES User Guide

ID 721819
Date 11/30/2022

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6.1.2. FPGA Timing Analysis

When you generate the LVDS SERDES IP, the IP generates the SERDES hardware clock settings and the core clock for IP timing analysis.
Table 34.  Clocks for the Transmitter and Receiver in Non-DPA and DPA-FIFO ModesBecause the frequency of LVDS fast clock is higher than the user core clock by the serialization factor, the IP also creates multicycle path constraints for proper timing analysis at the SERDES–core interface.
Clock Clock Name
Core clock <pll_instance_name>_*_outclk[*]
LVDS fast clock <pll_instance_name>_*_lvds_clk[*]
Table 35.  Clock for the Receiver in Soft-CDR Mode
Clock Clock Name
Core clock <lvds_instance_name>_core_ck_name_<channel_num>
DPA fast clock <lvds_instance_name>_dpa_ck_name_<channel_num>
To ensure proper timing analysis, instead of multicycle constraints, the IP creates clock settings at rx_out in the following format:
  • For rising edge data— <lvds_instance_name>_core_data_out_<channel_num>_<bit>
  • For falling edge data— <lvds_instance_name>_core_data_out_<channel_num>_<bit>_neg

With these proper clock settings, the Timing Analyzer can correctly analyze the timing of the LVDS SERDES–core interface transfer and within the core transfer.