7.1. LVDS SERDES IP Synthesizable Intel® Quartus® Prime Design Examples
The design example uses the parameter settings you configured in the IP parameter editor:
- Basic LVDS SERDES IP system with transmitters or receivers
- LVDS SERDES IP system with transmitters or receivers connected to an external PLL
If you configured the IP to use an external PLL, the generated design example connects a properly configured IOPLL Intel® FPGA IP.
To demonstrate how to configure the PLL, the design example also provides the lvds_external_pll.qsys Platform Designer file containing a standalone version of the IOPLL IP configured to work as an external PLL. You can use lvds_external_pll.qsys, modified or unmodified, to build an LVDS design with external PLL.
Generating and Using the Design Example
To generate the synthesizable Intel® Quartus® Prime design example from the source files, run the following command in the design example directory:
quartus_sh -t make_qii_design.tcl -system ed_synth
The TCL script creates a qii directory that contains the ed_synth.qpf project file. You can open and compile this project in the Intel® Quartus® Prime software.
For more information about make_qii_design.tcl arguments, run the following command:
quartus_sh -t make_qii_design.tcl -help
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