Intel® Agilex™ F-Series and I-Series LVDS SERDES User Guide

ID 721819
Date 11/30/2022
Public
Document Table of Contents

3.4.1. Transmitter Output Clock Parameters Settings

You can refer to the Clock Resource Summary tab in the LVDS SERDES IP parameter editor for information about configuring and connecting an external PLL to the LVDS SERDES IP.

The Clock Resource Summary tab lists the required settings you need for the IOPLL Intel® FPGA IP:

  • Frequencies, phase shifts, and duty cycles of the required clocks
  • Instructions for connections and the compensation mode

You can specify the relationship of tx_outclock to the tx_out data using these parameters:

  • Desired tx_outclock phase shift (degrees)
  • Tx_outclock division factor

The parameters set the phase and frequency of the tx_outclock based on the fast_clock, which operates at the serial data rate. You can set the tx_outclock frequency by selecting the available division factors.

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