4.3.3. Soft-CDR Mode
In the soft-CDR mode, the synchronizer block is inactive. The DPA circuitry selects an optimal DPA clock phase to sample the data. The receiver uses the selected clock for bit slip operation and deserialization.
Additionally, the DPA block divides the selected DPA clock by the deserialization factor and forwards it as rx_divfwdclk together with the deserialized data to the FPGA fabric. The rx_divfwdclk clock signal resides in the periphery clock (PCLK) network.
If you use the soft-CDR mode, do not assert the rx_dpa_reset signal after the DPA has been trained. The DPA continuously chooses new phase taps from the PLL to track parts per million (PPM) differences between the reference clock and incoming data.
In the soft-CDR mode, the rx_dpa_locked signal is invalid because the DPA continuously changes its phase to track PPM differences between the upstream transmitter and the local receiver input reference clocks. However, you can use the rx_dpa_locked signal to determine the initial DPA locking conditions that indicate the DPA has selected the optimal phase tap to capture the data. The rx_dpa_locked signal deasserts when the receiver operates in the soft-CDR mode. The receiver also forwards the rx_divfwclk parallel clock, generated from the DPA clock, to the FPGA fabric.
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