Intel® Agilex™ F-Series and I-Series LVDS SERDES User Guide

ID 721819
Date 11/30/2022
Public
Document Table of Contents

3.4.1.1. Edge-Aligned tx_outclock to tx_out

For rising tx_outclock edge-aligned to the MSB of the serial data on tx_out, specify a 0° phase shift.
Figure 8.  0° Edge Aligned tx_outclock ×8 Serializer Waveform with a Division Factor of 8


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