Intel® Agilex™ F-Series and I-Series LVDS SERDES User Guide

ID 721819
Date 11/30/2022
Public
Document Table of Contents

9. Intel® Agilex™ F-Series and I-Series High-Speed SERDES Troubleshooting Guidelines

These debug guidelines are initial debug actions and do not necessarily resolve the failures in your designs.
Table 37.  High-speed SERDES I/O Debug GuidelinesThis table lists the failure symptoms and the associated debug actions that you can take to identify the failure areas when designing high-speed SERDES systems with Intel® Agilex™ devices.
Failure Symptoms Recommended Debug Actions

pll_locked signal is unable to assert

  • Ensure that the pll_areset signal is deasserted.
  • If you are using the LVDS SERDES IP with the external PLL mode, ensure that the desired PLL IP settings match the recommended settings from the LVDS SERDES IP Clock Resource Summary tab.
    Note: Use simple PLL settings when debugging this failure to limit the failure scope. Ensure that the external PLL automatic switchover and dynamic reconfiguration modes are disabled.
  • Switch to use internal PLL to verify if the same failure occurs when using internal PLL.

rx_dpa_locked signal is unable to assert

  • Ensure that the pll_locked signal is asserted and the rx_dpa_reset is deasserted. It is important to ensure that the PLL is able to lock to confirm that the LVDS SERDES IP input clock frequency is correct.
  • Provide a training pattern to the DPA block with a toggling signal that conforms to the LVDS input buffer specification.

Random bit error occurs at LVDS receiver parallel data out bus

  • Ensure that RD termination is applied. You can enable OCT RD using the assignment editor in the Intel® Quartus® Prime software or place an on-board 100 Ω resistor termination. Refer to the related information.
  • Measure the rx_in_p and rx_in_n signal voltages and ensure that the voltages conforms to the VID and VICM requirements.
  • If the rx_in_p and rx_in_n signals have jitter, ensure that the signals have sufficient data valid window that conforms to the sampling window requirements.
  • Re-initialize the LVDS receiver reset sequence and ensure that:
    • The pll_locked signal is asserted.
    • The rx_dpa_locked signal is asserted.
    • The rx_fifo_reset signal is deasserted after FIFO reset (for DPA FIFO mode only).
    • The rx_divfwdclk (soft-CDR mode only) and rx_coreclock signals have the correct clock frequencies ( ).

LVDS receiver parallel data out is not matching a training pattern

Assert the rx_bitslip_ctrl signal for one clock cycle to add bit latency to the received bitstream. Continue to assert the signal until you see the expected pattern at the rx_out bus.

The rx_bitslip_max signal asserts before it reaches the bit slip rollover value

  • Check the bit slip rollover value in the LVDS SERDES IP. Set the rollover value based on .
  • Assert the rx_bitslip_reset signal before starting the bit slip and the reset must hold for at least one parallel clock cycle (based on rx_coreclock or rx_divfwdck).

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