1. Intel® Agilex™ F-Series and I-Series LVDS SERDES Overview 2. Intel® Agilex™ F-Series and I-Series High-Speed SERDES Architecture 3. Intel® Agilex™ LVDS SERDES Transmitter 4. Intel® Agilex™ LVDS SERDES Receiver 5. Intel® Agilex™ High-Speed LVDS I/O Implementation Guide 6. Intel® Agilex™ LVDS SERDES Timing 7. LVDS SERDES Intel® FPGA IP Design Examples 8. Intel® Agilex™ F-Series and I-Series High-Speed SERDES Design Guidelines 9. Intel® Agilex™ F-Series and I-Series High-Speed SERDES Troubleshooting Guidelines 10. Documentation Related to the Intel® Agilex™ F-Series and I-Series LVDS SERDES User Guide 11. Document Revision History for the Intel® Agilex™ F-Series and I-Series LVDS SERDES User Guide
2.1. Intel® Agilex™ GPIO Banks, SERDES, and DPA Locations
The GPIO banks are located at the top and bottom I/O bank rows.
Figure 1. Intel® Agilex™ I/O Bank Structure (Die Top View)This figure shows the I/O bank structure of the Intel® Agilex™ device. The figure shows the view of the die, as shown in the Intel® Quartus® Prime Chip Planner. In the Pin Planner, the view is flipped. Different device packages have different number of I/O banks. Refer to the device pin-out files for available I/O banks and the locations of the SDM and HPS shared I/O banks for each device package.
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