Intel® Agilex™ F-Series and I-Series LVDS SERDES User Guide

ID 721819
Date 11/30/2022
Document Table of Contents

2.1. Intel® Agilex™ GPIO Banks, SERDES, and DPA Locations

The GPIO banks are located at the top and bottom I/O bank rows.
Figure 1.  Intel® Agilex™ I/O Bank Structure (Die Top View)This figure shows the I/O bank structure of the Intel® Agilex™ device. The figure shows the view of the die, as shown in the Intel® Quartus® Prime Chip Planner. In the Pin Planner, the view is flipped. Different device packages have different number of I/O banks. Refer to the device pin-out files for available I/O banks and the locations of the SDM and HPS shared I/O banks for each device package.

Did you find the information on this page useful?

Characters remaining:

Feedback Message