The first set of registers captures the parallel data from the core using the LVDS fast clock. Together with the LVDS fast clock, the system provides the load_enable clock to enable these capture registers once in each coreclock period.
After the load registers capture the data, the serializer loads the data into a shift register that shifts the LSB towards the MSB at one bit per fast clock cycle. The MSB of the shift register feeds the LVDS output buffer. Consequently, higher order bits precede lower order bits in the output bitstream.
Data for serialization
(Supported serialization factors: 3–10)
|fast_clock||Clock for the transmitter|
|load_enable||Enable signal for serialization|
|tx_out||LVDS output data stream|
Did you find the information on this page useful?