Intel® Agilex™ F-Series and I-Series LVDS SERDES User Guide

ID 721819
Date 11/30/2022
Public
Document Table of Contents

3.2. Serializer

The serializer consists of two sets of registers.

The first set of registers captures the parallel data from the core using the LVDS fast clock. Together with the LVDS fast clock, the system provides the load_enable clock to enable these capture registers once in each coreclock period.

After the load registers capture the data, the serializer loads the data into a shift register that shifts the LSB towards the MSB at one bit per fast clock cycle. The MSB of the shift register feeds the LVDS output buffer. Consequently, higher order bits precede lower order bits in the output bitstream.

Figure 4.  LVDS SERDES ×8 Serializer Bit PositionThis figure shows the waveform specific to the serialization factor of eight.
Table 5.  LVDS SERDES Serializer Signals
Signal Description
tx_in[7:0]

Data for serialization

(Supported serialization factors: 3–10)

fast_clock Clock for the transmitter
load_enable Enable signal for serialization
tx_out LVDS output data stream

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