Intel® Agilex™ F-Series and I-Series LVDS SERDES User Guide

ID 721819
Date 11/30/2022
Public
Document Table of Contents

3.3. Differential I/O Bit Position

Successful high frequencies data transmission requires data synchronization.
Figure 6. Bit-Order and Word Boundary for One Differential Channel

This figure shows the data bit orientation for a channel operation, based on the following conditions:

  • The serialization factor is equal to the clock multiplication factor.
  • The phase alignment uses edge alignment.
  • The operation is implemented in the hard SERDES.
Table 7.  Differential Bit NamingThis table lists the differential bit naming conventions for 12 differential channels. The MSB and LSB positions increase with the number of channels a system uses.
Transmitter Channel Data Number Internal 8-Bit Parallel Data
MSB Position LSB Position
1 7 0
2 15 8
3 23 16
4 31 24
5 39 32
6 47 40
7 55 48
8 63 56
9 71 64
10 79 72
11 87 80
12 95 88

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