Intel® Agilex™ F-Series and I-Series LVDS SERDES User Guide

ID 721819
Date 11/30/2022
Public
Document Table of Contents

5.1.5.4. LVDS SERDES Intel® FPGA IP Transmitter Settings

The parameter options in the Transmitter Settings tab are available if you select the TX functional mode in the General Settings tab.
Table 19.  Transmitter Settings Tab
Parameter Value Description
Enable tx_coreclock port
  • On
  • Off

Turn on to expose the tx_coreclock port that you can use to drive the core logic feeding the transmitter.

Default is On.

Intel recommends that you use the tx_coreclock output signal if it is requested.

Note: This option is disabled if the Use external PLL option in the PLL Settings tab is turned on. To expose the tx_coreclock when using external PLL, turn off Use external PLL option before turning on the Enable tx_coreclock port. After making changes to Enable tx_coreclock port, you can turn Use external PLL back on.
Enable tx_outclock port
  • On
  • Off

Turn on to expose the tx_outclock port.

Default is On.

  • The tx_outclock port frequency depends on the setting for the Tx_outclock division factor parameter.
  • The phases of the tx_outclock_p and tx_outclock_n ports depend on the Desired tx_outclock phase shift parameter.

Turning on this parameter reduces the maximum number of channels per transmitter interface by one channel.

Desired tx_outclock phase shift (degrees)
  • 0
  • 180
  • 360

Specifies the phase relationship between the outclock and outgoing serial data in degrees of the LVDS fast clock.

Default is 0.

Actual tx_outclock phase shift (degrees)

Depends on the Desired tx_outclock phase shift (degrees) input. Refer to related information.

Displays the closest achievable tx_outclock phase shift to the desired tx_outclock phase shift.

Tx_outclock division factor Depends on the SERDES factor. Specifies the ratio of the fast clock frequency to the outclock frequency. For example, the maximum number of serial transitions per outclock cycle.

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