Intel® Agilex™ F-Series and I-Series LVDS SERDES User Guide

ID 721819
Date 11/30/2022
Public
Document Table of Contents

3.1. LVDS SERDES Transmitter Blocks

In the Intel® Agilex™ LVDS SERDES transmitter, the serializer receives up to 10 bits wide parallel data from the FPGA fabric.
Figure 3. LVDS SERDES Transmitter
  • The serializer clocks the data into the load registers and serializes the data using shift registers.
  • The I/O PLL that drives the data to the differential buffer clocks the shift registers.
  • The shift registers transmit the MSB of the parallel data first.
Note: The PLL that drives the SERDES channel must operate in integer PLL mode. You do not need a PLL if you bypass the serializer.

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