Intel® Agilex™ F-Series and I-Series LVDS SERDES User Guide

ID 721819
Date 11/30/2022
Public
Document Table of Contents

5.1.4. Generating the LVDS SERDES Intel® FPGA IP

Using the LVDS SERDES Intel® FPGA IP parameter editor, you can customize the IP settings and generate the IP variant files, simulation testbench, and HDL instantiation template.
Before you begin, create or open an Intel® Quartus® Prime project.
Figure 22.  LVDS SERDES Intel FPGA IP Parameter Editor
  1. In the IP Catalog window, double-click LVDS SERDES Intel® FPGA IP .
    The Parameter Editor window appears.
  2. Specify a top-level name for your new IP variant and click Create.
    Do not include space and special characters in the name and file path.
  3. Set the values in the Parameters tab.
    The System Messages tab displays errors and warning for the parameters settings.
  4. From the Parameter Editor menu, select File > Save.
    The parameter editor saves the IP variant settings in the <your_ip> .ip file.
  5. To generate the IP variant HDL files:
    1. Click Generate HDL.
      The Generation window appears.
    2. Specify the output file generation options and click Generate.
      The parameter editor generates the synthesis and simulation files as you specified, and automatically adds the .ip file of the variant to your project.
    3. Click Close.
  6. To generate a simulation testbench:
    1. From the Parameter Editor menu, select Generate > Generate Testbench System.
    2. Specify the testbench generation options and click Generate.
    3. Click Close.
  7. To generate an HDL instantiation template that you can copy and paste into your text editor:
    1. From the Parameter Editor menu, select Generate > Show Instantiation Template.
    2. Select the HDL Language.
      The code template appears in the Example HDL box.
    3. Click Copy and then click Close.
After generating and instantiating your IP variant, assign appropriate pins to connect the ports.

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