Intel® Agilex™ F-Series and I-Series LVDS SERDES User Guide

ID 721819
Date 11/30/2022

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3.4. Clocking the Differential Transmitters

The I/O PLL generates the fast_clock and load_enable signals.
  • The fast_clock signal clocks the load and shift registers, and runs at the serial data rate.
  • The system derives the load_enable signal from the serialization factor setting. You can statically set the serialization factor from ×3 to ×10 using the LVDS SERDES Intel® FPGA IP parameter editor.

You can configure any Intel® Agilex™ transmitter data channel to generate a source-synchronous transmitter clock output. This allows placement of the output clock near the data outputs to simplify board layout and reduce clock-to-data skew.

Figure 7. Transmitter in Clock Output Mode

Different applications often require specific clock-to-data alignments or specific data-rate-to-clock-rate factors. You can specify these settings statically in the LVDS SERDES Intel® FPGA IP parameter editor:

  • The transmitter can output a clock signal at the same rate as the data with a maximum output clock frequency supported by the device speed grade.
  • You can divide the output clock by a factor of 1, 2, 4, 6, 8, or 10, depending on the serialization factor.
  • You can set the phase of the clock in relation to the data at 0° (edge-aligned) or 180° (center-aligned). The I/O PLLs provide additional support for other phase shifts in 45° increments.