Intel® Agilex™ F-Series and I-Series LVDS SERDES User Guide

ID 721819
Date 11/30/2022
Public
Document Table of Contents

4.1. LVDS SERDES Receiver Blocks

The True Differential Signaling buffer can receive LVDS, mini-LVDS, RSDS, and LVPECL compatible signaling. You can statically set the I/O standard of the receiver pins to True Differential Signaling in the Intel® Quartus® Prime Assignment Editor or .qsf file.
Figure 11. Receiver Block DiagramThis figure shows the hardware blocks of the receiver. In SDR and DDR modes, the data width from the IOE is 1 and 2 bits, respectively. The deserializer includes shift registers and parallel load registers, and sends a maximum of 10 bits to the internal logic.
Note: The PLL that drives the SERDES channel must operate in integer PLL mode. You do not need a PLL if you bypass the deserializer

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