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1. Intel® Agilex™ F-Series and I-Series LVDS SERDES Overview
2. Intel® Agilex™ F-Series and I-Series High-Speed SERDES Architecture
3. Intel® Agilex™ LVDS SERDES Transmitter
4. Intel® Agilex™ LVDS SERDES Receiver
5. Intel® Agilex™ High-Speed LVDS I/O Implementation Guide
6. Intel® Agilex™ LVDS SERDES Timing
7. LVDS SERDES Intel® FPGA IP Design Examples
8. Intel® Agilex™ F-Series and I-Series High-Speed SERDES Design Guidelines
9. Intel® Agilex™ F-Series and I-Series High-Speed SERDES Troubleshooting Guidelines
10. Documentation Related to the Intel® Agilex™ F-Series and I-Series LVDS SERDES User Guide
11. Document Revision History for the Intel® Agilex™ F-Series and I-Series LVDS SERDES User Guide
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4. Intel® Agilex™ LVDS SERDES Receiver
The Intel® Agilex™ LVDS SERDES receivers are dedicated circuitries.
Each dedicated receiver circuitry consists of:
- A true differential buffer
- A deserializer
- I/O PLLs that you can share between the SERDES transmitter and receiver
- A data realignment block (bit slip)
- A data phase alignment (DPA) block
- A synchronizer
Dedicated Circuitry / Feature | Description |
---|---|
Differential I/O buffer | Supports True Differential Signaling I/O standard, which is compatible with LVDS, RSDS, Mini-LVDS, and LVPECL |
SERDES | Up to 10-bit wide deserializer |
Phase-locked loops (PLLs) | Generates different phases of a clock for data synchronizer |
Data realignment (bit slip) | Inserts bit latencies into serial data |
Dynamic phase alignment (DPA) | Chooses a phase closest to the phase of the serial data |
Synchronizer (FIFO buffer) | Compensate for phase differences between the data and the receiver’s input reference clock |
Skew adjustment | Manual |
On-chip termination (OCT) | 100 Ω in True Differential Signaling I/O standards |