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1. Intel® Agilex™ F-Series and I-Series LVDS SERDES Overview
2. Intel® Agilex™ F-Series and I-Series High-Speed SERDES Architecture
3. Intel® Agilex™ LVDS SERDES Transmitter
4. Intel® Agilex™ LVDS SERDES Receiver
5. Intel® Agilex™ High-Speed LVDS I/O Implementation Guide
6. Intel® Agilex™ LVDS SERDES Timing
7. LVDS SERDES Intel® FPGA IP Design Examples
8. Intel® Agilex™ F-Series and I-Series High-Speed SERDES Design Guidelines
9. Intel® Agilex™ F-Series and I-Series High-Speed SERDES Troubleshooting Guidelines
10. Documentation Related to the Intel® Agilex™ F-Series and I-Series LVDS SERDES User Guide
11. Document Revision History for the Intel® Agilex™ F-Series and I-Series LVDS SERDES User Guide
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4.2.1. Receiver Input Clock Parameters Settings
To sample the source-synchronous data using the SERDES receiver in non-DPA mode, specify the phase relationship between the inclock signal and the rx_in data.
You can specify the inclock to rx_in phase relationship value in the Desired receiver inclock phase shift (degrees) parameter setting.
The phase relationship value must be evenly divisible by 45. If the value is not divisible by 45, the actual phase shift appears in the Actual receiver inclock phase shift (degrees) parameter setting.
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