Intel® Agilex™ F-Series and I-Series LVDS SERDES User Guide

ID 721819
Date 11/30/2022
Document Table of Contents

4.2.1. Receiver Input Clock Parameters Settings

To sample the source-synchronous data using the SERDES receiver in non-DPA mode, specify the phase relationship between the inclock signal and the rx_in data.

You can specify the inclock to rx_in phase relationship value in the Desired receiver inclock phase shift (degrees) parameter setting.

The phase relationship value must be evenly divisible by 45. If the value is not divisible by 45, the actual phase shift appears in the Actual receiver inclock phase shift (degrees) parameter setting.

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