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1. Intel® Agilex™ F-Series and I-Series LVDS SERDES Overview
2. Intel® Agilex™ F-Series and I-Series High-Speed SERDES Architecture
3. Intel® Agilex™ LVDS SERDES Transmitter
4. Intel® Agilex™ LVDS SERDES Receiver
5. Intel® Agilex™ High-Speed LVDS I/O Implementation Guide
6. Intel® Agilex™ LVDS SERDES Timing
7. LVDS SERDES Intel® FPGA IP Design Examples
8. Intel® Agilex™ F-Series and I-Series High-Speed SERDES Design Guidelines
9. Intel® Agilex™ F-Series and I-Series High-Speed SERDES Troubleshooting Guidelines
10. Documentation Related to the Intel® Agilex™ F-Series and I-Series LVDS SERDES User Guide
11. Document Revision History for the Intel® Agilex™ F-Series and I-Series LVDS SERDES User Guide
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5.3.4.1. Aligning Word Boundaries
After initializing the LVDS SERDES IP in DPA or non-DPA mode, perform these steps to align the word boundaries.
- Assert the rx_bitslip_reset port for at least one parallel clock cycle, and then deassert the rx_bitslip_reset port.
- Begin word alignment by applying pulses as required to the rx_bitslip_ctrl port.
After the word boundaries are established on each channel, the interface is ready for operation.