Intel® Agilex™ F-Series and I-Series LVDS SERDES User Guide

ID 721819
Date 11/30/2022
Public
Document Table of Contents

8.5. Placing LVDS Transmitters and Receivers in the Same GPIO Bank

If you want to place both LVDS transmitter and receiver interfaces in the same GPIO bank, use an external PLL.
  • To use an external PLL, in the LVDS SERDES IP parameter editor, turn on the Use external PLL option.
  • You can generate two instances of the LVDS SERDES IP—a receiver and a transmitter.
  • In each instance, you can use up to the following number of channels:
    • 12 transmitters
    • 11 DPA or non-DPA receivers, with one inclock for the I/O PLL
    • 8 soft-CDR receivers
  • Generate the IOPLL Intel FPGA IP and ensure that the .qsf file lists the IOPLL IP before the LVDS SERDES IP. This order is required for your design to compile with the proper clock constraints.
  • Connect the same PLL to both the transmitter and receiver instances. You can either use the tx_coreclock from the LVDS transmitter instance or the rx_coreclock from the LVDS receiver instance to clock your core logic. For the RX Soft-CDR mode, connect the tx_coreclock of the LVDS transmitter instance to the ext_coreclock port of the LVDS receiver instance.
  • Set the I/O standard for the refclk port of the IOPLL IP to be compatible with the I/O standard used by the LVDS SERDES IP.

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