Intel® Agilex™ F-Series and I-Series LVDS SERDES User Guide

ID 721819
Date 11/30/2022
Public
Document Table of Contents

5.3.1. Initializing the LVDS SERDES IP in Non-DPA Mode

The PLL is operational after it achieves lock in user mode. Before transferring data using SERDES block with the LVDS SERDES IP, ensure that the PLL is locked to the reference clock.

Intel recommends that you follow these steps to initialize the LVDS SERDES IP in non-DPA mode:

  1. During entry into user mode, assert the pll_areset signal for at least 10 ns.
    You can also perform this step at any time in user mode operation to reset the interface.
  2. After at least 10 ns, deassert the pll_areset signal and monitor the pll_locked port.
    In the external PLL mode, you may observe a delay between the assertion of the ext_pll_locked and pll_locked signals. The ext_pll_locked signal asserts when the external PLL locks while the pll_locked signal asserts after the external PLL and CPA lock. Always use the pll_locked signal to determine if the SERDES block is ready for operation.

After the PLL lock port from the LVDS SERDES IP asserts and becomes stable, the SERDES blocks are ready for operation.

After the initialization, you can proceed to align the word boundaries (bit slip).

Did you find the information on this page useful?

Characters remaining:

Feedback Message