Intel® Agilex™ F-Series and I-Series LVDS SERDES User Guide

ID 721819
Date 11/30/2022
Public
Document Table of Contents

4.1.4. Deserializer

The deserializer includes shift registers and parallel load registers. The deserializer sends a maximum of 10 bits to the internal logic. You can statically set the deserialization factor from ×3 to ×10 in the LVDS SERDES Intel® FPGA IP parameter editor.

The I/O element (IOE) contains two data input registers. Each data input register can operate in double data rate (DDR) or single data rate (SDR) mode. Use the GPIO Intel® FPGA IP to bypass the serializer and operate in DDR and SDR modes.

If you bypass the deserializer, you cannot use the DPA block and data realignment circuit.

Figure 15. Deserializer BypassThis figure shows the deserializer bypass path.
Table 8.  SDR and DDR Receiver Modes
Mode Description
SDR (×1)
  • The IOE data width is 1 bit.
  • Deserialization factor of 1.
  • Registered input path requires a clock.
  • Data is passed directly through the IOE.
DDR (×2)
  • The IOE data width is 2 bits.
  • Deserialization factor of 2.
  • The GPIO IP requires a clock.
  • rx_inclock clocks the IOE register. The clock must be synchronous to rx_in.
  • You must control the data-to-clock skew.

Did you find the information on this page useful?

Characters remaining:

Feedback Message