Intel® Agilex™ F-Series and I-Series LVDS SERDES User Guide

ID 721819
Date 11/30/2022
Public
Document Table of Contents

5.3. LVDS SERDES IP Initialization and Reset

During device initialization, the clock reference must be stable while the PLL is locking to it to avoid corruption of the PLL output clock phase shifts. If the output clock phase shifts are incorrect, data transfer between the high-speed LVDS and low-speed parallel domain can fail and causes corrupted data.

After you have initialized the IP in DPA or non-DPA mode, you can perform word boundaries alignment using the bit slip control signal.

Note: Intel requires that you include the Reset Release Intel® FPGA IP in your design to hold your application logic in the reset state until the entire FPGA fabric enters user mode.

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