Intel® Agilex™ F-Series and I-Series LVDS SERDES User Guide

ID 721819
Date 11/30/2022
Public
Document Table of Contents

3.4.1.2. Center-Aligned tx_outclock to tx_out

To specify a center-aligned relationship between tx_outclock and the MSB of the serial data on tx_out, specify a 180° phase shift.
Figure 9.  180° Center Aligned tx_outclock ×8 Serializer Waveform with a Division Factor of 8


  • Phase shift values from 0° to 315° position the rising edge of tx_outclock within the MSB of the tx_out data.
  • Phase shift values starting from 360° position the rising edge of tx_outclock in serial bits after the MSB. For example, a 540° phase shift positions the rising edge in the center of the bit after the MSB.
Figure 10.  180° Center Aligned tx_outclock ×8 Serializer Waveform with Division Factor of 2This figure shows a ×8 serialization factor using a 180° phase shift with a tx_outclock division factor of 2 (DDR clock and data relationship).


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