Intel® Agilex™ F-Series and I-Series LVDS SERDES User Guide

ID 721819
Date 11/30/2022
Public
Document Table of Contents

11. Document Revision History for the Intel® Agilex™ F-Series and I-Series LVDS SERDES User Guide

Document Version Intel® Quartus® Prime Version Changes
2022.11.30 22.1
  • Updated the VCO Frequency information in Table: Example: Generating Output Clocks Using an IOPLL IP (Receiver in DPA or Soft-CDR Mode)
2022.06.09 22.1

Updated the topic about placing LVDS transmitters and receivers in the same GPIO bank to add related information links to information about true differential signaling I/O standard specifications and termination.

2022.03.28 22.1
  • Initial release.
    • Moved the contents from the Intel® Agilex™ General-Purpose I/O and LVDS SERDES User Guide.
    • Restructured and rewritten the contents to improve ease of reference and modularity.
    • Updated the LVDS SERDES IP receiver settings to include the RCCS parameter.
    • Corrected the figure showing the basic LVDS SERDES IP system with internal PLL. The LVDS SERDES IP for Intel® Agilex™ F-series and I-series devices does not support the duplex feature.
    • Updated the guidelines for placing LVDS transmitters and receivers in the same GPIO bank to specify that you can only place 11 DPA or non-DPA receivers. You need one channel in the sub-bank for the I/O PLL reference clock input.
Note: For the history of previous revisions and to access previous versions of this user guide, refer to the Intel® Agilex™ F-Series and I-Series General-Purpose I/O User Guide.

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