Intel® Agilex™ F-Series and I-Series LVDS SERDES User Guide

ID 721819
Date 11/30/2022
Public
Document Table of Contents

4.2.1.1. Edge-Aligned inclock to rx_in

For rising inclock edge-aligned to the rx_in data, specify 0° as the desired receiver clock phase shift. Specifying 0° phase shift sets the PLL with the required phase shift from fast_clock to center it at the SERDES receiver.
Figure 16.  0° Edge-Aligned inclock ×8 Deserializer Waveform with a Single Rate Clock


The phase shift you specify is relative to the fast_clock, which operates at the serial data rate. Use phase shift values between 0° and 360° to specify the rising edge of the inclock within a single bit period. If you specify phase shift values greater than 360°, the MSB location within the parallel data changes.

Equation 1. Maximum Phase Shift ValueThis equation determines the maximum phase shift value.

(Number of fast_clock periods per inclock period × 360) – 1

Note: By default, the MSB from the serial data is not the MSB of the parallel data. You can use the bit slip to set the proper word boundary on the parallel data.

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