Intel® Agilex™ F-Series and I-Series LVDS SERDES User Guide

ID 721819
Date 11/30/2022
Public
Document Table of Contents

4.1.2. Synchronizer (DPA FIFO)

The synchronizer is a 1-bit wide and 6-bit deep FIFO buffer that compensates for the phase difference between dpa_fast_clock from the DPA block and the fast_clock that the I/O PLLs produce.

The synchronizer can compensate only for phase differences, not frequency differences, between the data and the input reference clock of the receiver.

The optional rx_fifo_reset signal resets the synchronizer. The synchronizer resets automatically when the DPA block first locks to the incoming data. If your data checker indicates corrupt received data, use rx_fifo_reset to reset the synchronizer.

Note: The receiver bypasses the synchronizer circuit in non-DPA and soft-CDR modes.

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