Intel® Agilex™ F-Series and I-Series LVDS SERDES User Guide

ID 721819
Date 11/30/2022
Public
Document Table of Contents

5.3.2. Initializing the LVDS SERDES IP in DPA Mode

The DPA circuit samples the incoming data and determines the optimal phase tap from the PLL to capture data at the receiver on a channel-by-channel basis. If the PLL has not locked to a stable clock source, the DPA circuit might lock prematurely to a non-ideal phase tap.

Before the PLL lock is stable, use the rx_dpa_reset signal to keep the DPA in reset. When the DPA has determined the optimal phase tap, the rx_dpa_locked signal asserts. The LVDS SERDES IP asserts the rx_dpa_locked port at the initial DPA lock. If you turn on the Enable DPA loss of lock on one change option, the rx_dpa_locked port deasserts after one phase change. If you turn off this option, the rx_dpa_locked signal deasserts after two phase changes in the same direction.

Intel recommends that you follow these steps to initialize and reset the LVDS SERDES IP in DPA mode:

  1. During entry into user mode, assert the pll_areset and rx_dpa_reset signals. Keep the pll_areset signal asserted for at least 10 ns.
    You can also perform this step at any time in user mode operation to reset the interface.
  2. After at least 10 ns, deassert the pll_areset signal and monitor the pll_locked port.
    In the external PLL mode, you may observe a delay between the assertion of the ext_pll_locked and pll_locked signals. The ext_pll_locked signal asserts when the external PLL locks while the pll_locked signal asserts after the external PLL and CPA lock. Always use the pll_locked signal to determine if the SERDES block is ready for operation.
  3. Deassert the rx_dpa_reset port after the pll_locked port from the LVDS SERDES IP becomes asserted and stable.
  4. Apply the DPA training pattern and allow the DPA circuit to lock.
    If a training pattern is not available, any data with transitions is required to allow the DPA to lock. For the DPA lock time specification, refer to the related information.
  5. After the rx_dpa_locked signal asserts, assert the rx_fifo_reset signal for at least one parallel clock cycle.
  6. To start receiving data, deassert the rx_fifo_reset signal.

During normal operation, every time the DPA shifts the phase taps to track variations between the reference clock source and the data, the data transfer timing margin between clock domains is reduced.

Note: To ensure data accuracy, Intel recommends that you use the data checkers.

After the initialization, you can proceed to align the word boundaries (bit slip).

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