1. Intel® Agilex™ F-Series and I-Series LVDS SERDES Overview 2. Intel® Agilex™ F-Series and I-Series High-Speed SERDES Architecture 3. Intel® Agilex™ LVDS SERDES Transmitter 4. Intel® Agilex™ LVDS SERDES Receiver 5. Intel® Agilex™ High-Speed LVDS I/O Implementation Guide 6. Intel® Agilex™ LVDS SERDES Timing 7. LVDS SERDES Intel® FPGA IP Design Examples 8. Intel® Agilex™ F-Series and I-Series High-Speed SERDES Design Guidelines 9. Intel® Agilex™ F-Series and I-Series High-Speed SERDES Troubleshooting Guidelines 10. Documentation Related to the Intel® Agilex™ F-Series and I-Series LVDS SERDES User Guide 11. Document Revision History for the Intel® Agilex™ F-Series and I-Series LVDS SERDES User Guide
5.3.3. Resetting the DPA
If data corruption occurs, reset the DPA circuitry.
- Assert the rx_dpa_reset signal to reset the entire DPA block. After you reset the entire DPA block, the DPA must be retrained before capturing data.
You can also fix data corruption by resetting only the synchronization FIFO without resetting the DPA circuit, which means that system operation continues without having to retrain the DPA. To reset just the synchronization FIFO, assert the rx_fifo_reset signal.
- After rx_dpa_locked asserts, the LVDS SERDES IP is ready to capture data. The DPA finds the optimal sample location to capture each bit.
Intel recommends that you toggle the rx_fifo_reset signal after rx_dpa_locked asserts. Toggling rx_fifo_reset ensures that the synchronization FIFO is set with the optimal timing to transfer data between the DPA and the high-speed LVDS clock domains.
- Using custom logic to control the rx_bitslip_ctrl signal on a channel-by-channel basis, set up the word boundary.
You can reset the bit slip circuit at any time, independent of the PLL or DPA circuit operation. To reset the bit slip circuit, use the rx_bitslip_reset signal.
Did you find the information on this page useful?