Intel® Agilex™ F-Series and I-Series LVDS SERDES User Guide

ID 721819
Date 11/30/2022

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Document Table of Contents

6.1.1. I/O Timing Analysis

Table 33.  Timing Analysis for Different LVDS SERDES IP Modes
Mode Timing Analysis

For LVDS transmitters, the Timing Analyzer provides the transmitter channel-to-channel skew (TCCS) value in the TCCS report (report_TCCS) in the Intel® Quartus® Prime compilation report. The TCCS report lists the TCCS values for serial output ports. You can also get the TCCS value from the device datasheet.

TCCS is the maximum skew observed across the channels of data and transmitter output clock—the difference between the fastest and slowest data output transitions, including the TCO variation and clock skew.


In non-DPA mode, use RSKM, TCCS, and sampling window (SW) specifications for high-speed source-synchronous differential signals in the receiver data path.

To obtain accurate RSKM results in the Timing Analyzer, add this line of code to your .sdc to specify the RCCS value:

set ::RCCS <RCCS value in nanoseconds>


set ::RCCS 0.0

The DPA hardware dynamically captures the received data in soft-CDR and DPA-FIFO modes. For these modes, the Timing Analyzer does not perform static I/O timing analysis.