Intel® Agilex™ F-Series and I-Series LVDS SERDES User Guide

ID 721819
Date 11/30/2022

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5.1.2. LVDS SERDES Intel® FPGA IP Features

The LVDS SERDES IP includes features for the LVDS receiver and transmitter. You can use the Intel® Quartus® Prime parameter editor to configure the LVDS SERDES IP.

The LVDS SERDES IP provides the following features for you to implement your LVDS I/O design:

  • Parameterizable data channel widths
  • Parameterizable SERDES factors
  • Registered input and output ports
  • PLL control signals
  • Non-DPA mode
  • DPA mode
  • Soft clock data recovery (CDR) mode
  • Clock phase alignment (CPA) block